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    Subject[PATCH 1/2 v4] MIPS: Ingenic: Fix bugs when detecting X1000's L2 cache.
    Date
    1.fix bugs when detecting L2 cache sets value.
    2.fix bugs when detecting L2 cache ways value.

    Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
    ---
    arch/mips/mm/sc-mips.c | 27 ++++++++++++++++++++-------
    1 file changed, 20 insertions(+), 7 deletions(-)

    diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
    index 9385ddb..dbdbfe5 100644
    --- a/arch/mips/mm/sc-mips.c
    +++ b/arch/mips/mm/sc-mips.c
    @@ -221,13 +221,26 @@ static inline int __init mips_sc_probe(void)
    else
    return 0;

    - /*
    - * According to config2 it would be 5-ways, but that is contradicted
    - * by all documentation.
    - */
    - if (current_cpu_type() == CPU_XBURST &&
    - mips_machtype == MACH_INGENIC_JZ4770)
    - c->scache.ways = 4;
    + if (current_cpu_type() == CPU_XBURST) {
    + switch (mips_machtype) {
    + /*
    + * According to config2 it would be 5-ways, but that is
    + * contradicted by all documentation.
    + */
    + case MACH_INGENIC_JZ4770:
    + c->scache.ways = 4;
    + break;
    +
    + /*
    + * According to config2 it would be 5-ways and 512-sets,
    + * but that is contradicted by all documentation.
    + */
    + case MACH_INGENIC_X1000:
    + c->scache.sets = 256;
    + c->scache.ways = 4;
    + break;
    + }
    + }

    c->scache.waysize = c->scache.sets * c->scache.linesz;
    c->scache.waybit = __ffs(c->scache.waysize);
    --
    2.7.4

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