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    Subject[PATCH 5.2 065/144] drm/amd/display: Clock does not lower in Updateplanes
    Date
    [ Upstream commit 492d9ec244923420af96db6b69ad7d575859aa92 ]

    [why]
    We reset the optimized_required in atomic_plane_disable
    flag immediately after it is set in atomic_plane_disconnect, causing us to
    never have flag set during next flip in UpdatePlanes.

    [how]
    Optimize directly after each time plane is removed.

    Signed-off-by: Murton Liu <murton.liu@amd.com>
    Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
    Acked-by: Leo Li <sunpeng.li@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++++++
    1 file changed, 6 insertions(+)

    diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
    index 9e4d70a0055e1..c7b4c3048b71d 100644
    --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
    +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
    @@ -2416,6 +2416,12 @@ static void dcn10_apply_ctx_for_surface(
    if (removed_pipe[i])
    dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);

    + for (i = 0; i < dc->res_pool->pipe_count; i++)
    + if (removed_pipe[i]) {
    + dc->hwss.optimize_bandwidth(dc, context);
    + break;
    + }
    +
    if (dc->hwseq->wa.DEGVIDCN10_254)
    hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
    }
    --
    2.20.1


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