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SubjectRe: [PATCH v6 8/8] KVM: x86: Add user-space access interface for CET MSRs
On Mon, Aug 12, 2019 at 04:43:36PM -0700, Sean Christopherson wrote:
> On Thu, Jul 25, 2019 at 11:12:46AM +0800, Yang Weijiang wrote:
> > There're two different places storing Guest CET states, the states
> > managed with XSAVES/XRSTORS, as restored/saved
> > in previous patch, can be read/write directly from/to the MSRs.
> > For those stored in VMCS fields, they're access via vmcs_read/
> > vmcs_write.
> >
> > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> > ---
> > arch/x86/kvm/vmx/vmx.c | 43 ++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 43 insertions(+)
> >
> > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> > index 123285177c6b..e5eacd01e984 100644
> > --- a/arch/x86/kvm/vmx/vmx.c
> > +++ b/arch/x86/kvm/vmx/vmx.c
> > @@ -1774,6 +1774,27 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> > else
> > msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
> > break;
> > + case MSR_IA32_S_CET:
> > + msr_info->data = vmcs_readl(GUEST_S_CET);
> > + break;
> > + case MSR_IA32_U_CET:
> > + rdmsrl(MSR_IA32_U_CET, msr_info->data);
> > + break;
> > + case MSR_IA32_INT_SSP_TAB:
> > + msr_info->data = vmcs_readl(GUEST_INTR_SSP_TABLE);
> > + break;
> > + case MSR_IA32_PL0_SSP:
> > + rdmsrl(MSR_IA32_PL0_SSP, msr_info->data);
> > + break;
> > + case MSR_IA32_PL1_SSP:
> > + rdmsrl(MSR_IA32_PL1_SSP, msr_info->data);
> > + break;
> > + case MSR_IA32_PL2_SSP:
> > + rdmsrl(MSR_IA32_PL2_SSP, msr_info->data);
> > + break;
> > + case MSR_IA32_PL3_SSP:
> > + rdmsrl(MSR_IA32_PL3_SSP, msr_info->data);
> > + break;
>
> These all need appropriate checks on guest and host support. The guest
> checks won't come into play very often, if ever, for the MSRs that exist
> if IBT *or* SHSTK is supported due to passing the MSRs through to the
> guest, but I don't think we want this code reliant on the interception
> logic. E.g.:
>
> case MSR_IA32_S_CET:
> if (!(host_xss & XFEATURE_MASK_CET_KERNEL))
> return 1;
>
> if (!msr_info->host_initiated &&
> !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) &&
> !guest_cpuid_has(vcpu, X86_FEATURE_IBT))
> return 1;
>
> MSR_IA32_U_CET is same as above, s/KERNEL/USER.
>
> case MSR_IA32_INT_SSP_TAB:
> if (!(host_xss & (XFEATURE_MASK_CET_KERNEL |
> XFEATURE_MASK_CET_USER)))
> return 1;
>
> if (!msr_info->host_initiated &&
> !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK))
> return 1;
>
> MSR_IA32_PL[0-3]_SSP are same as above, but only check the appropriate
> KERNEL or USER bit.
>
> Note, the PL[0-2]_SSP MSRs can be collapsed into a single case, e.g.:
>
> case MSR_IA32_PL0_SSP ... MSR_IA32_PL2_SSP:
> <error handling code>;
>
> rdmsrl(msr_index, msr_info->data);
> break;
>
>
> Rinse and repeat for vmx_set_msr().
>
Thanks you, will modify this part of code.

> > case MSR_TSC_AUX:
> > if (!msr_info->host_initiated &&
> > !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
> > @@ -2007,6 +2028,28 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> > else
> > vmx->pt_desc.guest.addr_a[index / 2] = data;
> > break;
> > + case MSR_IA32_S_CET:
> > + vmcs_writel(GUEST_S_CET, data);
> > + break;
> > + case MSR_IA32_U_CET:
> > + wrmsrl(MSR_IA32_U_CET, data);
> > + break;
> > + case MSR_IA32_INT_SSP_TAB:
> > + vmcs_writel(GUEST_INTR_SSP_TABLE, data);
> > + break;
> > + case MSR_IA32_PL0_SSP:
> > + wrmsrl(MSR_IA32_PL0_SSP, data);
> > + break;
> > + case MSR_IA32_PL1_SSP:
> > + wrmsrl(MSR_IA32_PL1_SSP, data);
> > + break;
> > + case MSR_IA32_PL2_SSP:
> > + wrmsrl(MSR_IA32_PL2_SSP, data);
> > + break;
> > + case MSR_IA32_PL3_SSP:
> > + wrmsrl(MSR_IA32_PL3_SSP, data);
> > + break;
> > +
> > case MSR_TSC_AUX:
> > if (!msr_info->host_initiated &&
> > !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
> > --
> > 2.17.2
> >

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