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SubjectRE: [PATCH V2 1/2] usb: dwc3: Add node to update cache type setting
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Hi Felipe

On Friday, July 26, 2019 11:30 Ran Wang wrote:
>
> Hi Felipe,
>
> On Friday, July 26, 2019 05:56, Rob Herring <robh@kernel.org> wrote:
> >
> > On Wed, Jul 24, 2019 at 8:29 PM Ran Wang <ran.wang_1@nxp.com> wrote:
> > >
> > > Hi Rob,
> > >
> > > On Thursday, July 25, 2019 04:42 Rob Herring <robh@kernel.org> wrote:
> > > >
> > > > On Fri, Jul 12, 2019 at 02:42:05PM +0800, Ran Wang wrote:
> > > > > Some Layerscape paltforms (such as LS1088A, LS2088A, etc)
> > > > > encounter USB detect failues when adding dma-coherent to DWC3
> > > > > node. This is because the HW default cache type configuration of
> > > > > those SoC are not right, need to be updated in DTS.
> > > > >
> > > > > Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> > > > > ---
> > > > > Change in v2:
> > > > > - New file.
> > > > >
> > > > > Documentation/devicetree/bindings/usb/dwc3.txt | 43
> > > > > ++++++++++++++++++++++++++
> > > > > 1 file changed, 43 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > > > > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > > > > index 8e5265e..7bc1cef 100644
> > > > > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > > > > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > > > > @@ -110,6 +110,43 @@ Optional properties:
> > > > > - in addition all properties from usb-xhci.txt from the current directory
> are
> > > > > supported as well
> > > > >
> > > > > +* Cache type nodes (optional)
> > > > > +
> > > > > +The Cache type node is used to tell how to configure cache type
> > > > > +on 4 different transfer types: Data Read, Desc Read, Data Write
> > > > > +and Desc write. For each treasfer type, controller has a 4-bit
> > > > > +register field to enable different cache type. Quoted from DWC3
> > > > > +data book Table 6-5
> > > > Cache Type Bit Assignments:
> > > > > +----------------------------------------------------------------
> > > > > +MBUS_TYPE| bit[3] |bit[2] |bit[1] |bit[0]
> > > > > +----------------------------------------------------------------
> > > > > +AHB |Cacheable |Bufferable |Privilegge |Data
> > > > > +AXI3 |Write Allocate|Read Allocate|Cacheable |Bufferable
> > > > > +AXI4 |Allocate Other|Allocate |Modifiable |Bufferable
> > > > > +AXI4 |Other Allocate|Allocate |Modifiable |Bufferable
> > > > > +Native |Same as AXI |Same as AXI |Same as AXI|Same as AXI
> > > > > +---------------------------------------------------------------
> > > > > +-
> > > > > +Note: The AHB, AXI3, AXI4, and PCIe busses use different names
> > > > > +for certain signals, which have the same meaning:
> > > > > + Bufferable = Posted
> > > > > + Cacheable = Modifiable = Snoop (negation of No Snoop)
> > > >
> > > > This should all be implied from the SoC specific compatible strings.
> > >
> > > Did you mean I could implement a soc driver which can be matched by
> > compatible of 'fsl,ls1088a-dwc3' which will pass known bus type to DWC3
> driver?
> > If yes, how to pass?
> >
> > Yes. The DT match table can have data associated with that compatible string.
> > Beyond that, I'm not really familiar with the DWC3 driver.
>
> Do you have any suggestion here?
> If I add a glue driver on DWC3 core driver (I know you are not happy on this way),
> I don't know how to pass the MBUS_TYPE info. from my glue driver to DWC3
> core driver (I think cache type related programming should be done by DWC3
> core driver, am I right?)

Or I add SoC specific handling code in DWC3 driver to do this cache type setting
according to SoC specific compatible strings
(such as compatible = "fsl,ls1088a-dwc3", "snps,dwc3";) ?

I know that so far DWC3 driver doesn't have any SoC specific handling code, this might be
the first one. Any comment or suggestion are welcome, thanks.

Regards,
Ran
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