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SubjectRe: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting
Hi Christoph,

On Tue, Aug 13, 2019 at 05:47:45PM +0200, Christoph Hellwig wrote:
> When we get booted we want a clear slate without any leaks from previous
> supervisors or the firmware. Flush the instruction cache and then clear
> all registers to known good values. This is really important for the
> upcoming nommu support that runs on M-mode, but can't really harm when
> running in S-mode either.

Sure.

> +#ifdef CONFIG_FPU

But it doesn't really mean that the running system has an FPU given CONFIG_FPU
enabled. Normally the existence of an FPU is checked in riscv_fill_hwcap by
searching device tree, where the code looks like


bool has_fpu = false; // this one is global
...
#ifdef CONFIG_FPU
if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
has_fpu = true;
#endif


Or does CONFIG_FPU have a more intuitive meaning when CONFIG_M_MODE is enabled?

> + csrr t0, CSR_MISA
> + andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
> + bnez t0, .Lreset_regs_done
> +
> + li t1, SR_FS
> + csrs CSR_XSTATUS, t1
> + fmv.s.x f0, zero
> + fmv.s.x f1, zero
> + fmv.s.x f2, zero
> + fmv.s.x f3, zero
> + fmv.s.x f4, zero
> + fmv.s.x f5, zero
> + fmv.s.x f6, zero
> + fmv.s.x f7, zero
> + fmv.s.x f8, zero
> + fmv.s.x f9, zero
> + fmv.s.x f10, zero
> + fmv.s.x f11, zero
> + fmv.s.x f12, zero
> + fmv.s.x f13, zero
> + fmv.s.x f14, zero
> + fmv.s.x f15, zero
> + fmv.s.x f16, zero
> + fmv.s.x f17, zero
> + fmv.s.x f18, zero
> + fmv.s.x f19, zero
> + fmv.s.x f20, zero
> + fmv.s.x f21, zero
> + fmv.s.x f22, zero
> + fmv.s.x f23, zero
> + fmv.s.x f24, zero
> + fmv.s.x f25, zero
> + fmv.s.x f26, zero
> + fmv.s.x f27, zero
> + fmv.s.x f28, zero
> + fmv.s.x f29, zero
> + fmv.s.x f30, zero
> + fmv.s.x f31, zero
> + csrw fcsr, 0
> + /* note that the caller must clear SR_FS */
> +#endif /* CONFIG_FPU */

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