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SubjectRe: [PATCH v4 8/9] MIPS: SGI-IP27: fix readb/writeb addressing
On Sat, Aug 10, 2019 at 04:22:23PM +0300, Andy Shevchenko wrote:
> On Fri, Aug 9, 2019 at 1:34 PM Thomas Bogendoerfer
> <tbogendoerfer@suse.de> wrote:
> >
> > Our chosen byte swapping, which is what firmware already uses, is to
> > do readl/writel by normal lw/sw intructions (data invariance). This
> > also means we need to mangle addresses for u8 and u16 accesses. The
> > mangling for 16bit has been done aready, but 8bit one was missing.
> > Correcting this causes different addresses for accesses to the
> > SuperIO and local bus of the IOC3 chip. This is fixed by changing
> > byte order in ioc3 and m48rtc_rtc structs.
>
> > /* serial port register map */
> > struct ioc3_serialregs {
> > - uint32_t sscr;
> > - uint32_t stpir;
> > - uint32_t stcir;
> > - uint32_t srpir;
> > - uint32_t srcir;
> > - uint32_t srtr;
> > - uint32_t shadow;
> > + u32 sscr;
> > + u32 stpir;
> > + u32 stcir;
> > + u32 srpir;
> > + u32 srcir;
> > + u32 srtr;
> > + u32 shadow;
> > };
>
> Isn't it a churn? AFAIU kernel documentation the uint32_t is okay to
> use, just be consistent inside one module / driver.
> Am I mistaken?

No, but really it uint* shouldn't be used anywhere in the kernel source
as it does not make sense.

thanks,

greg k-h

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