Messages in this thread | | | Subject | Re: [PATCH bpf-next] Enable zext optimization for more RV64G ALU ops | From | Daniel Borkmann <> | Date | Sat, 6 Jul 2019 00:01:13 +0200 |
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On 07/05/2019 02:18 AM, Luke Nelson wrote: > commit 66d0d5a854a6 ("riscv: bpf: eliminate zero extension code-gen") > added the new zero-extension optimization for some BPF ALU operations. > > Since then, bugs in the JIT that have been fixed in the bpf tree require > this optimization to be added to other operations: commit 1e692f09e091 > ("bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh"), > and commit fe121ee531d1 ("bpf, riscv: clear target register high 32-bits > for and/or/xor on ALU32") > > Now that these have been merged to bpf-next, the zext optimization can > be enabled for the fixed operations. > > Cc: Song Liu <liu.song.a23@gmail.com> > Cc: Jiong Wang <jiong.wang@netronome.com> > Cc: Xi Wang <xi.wang@gmail.com> > Signed-off-by: Luke Nelson <luke.r.nels@gmail.com>
Applied, thanks!
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