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    Subject[PATCH v5 17/20] PM / devfreq: tegra30: Increase sampling period to 16ms
    Date
    Increase sampling period by 4ms to get a nicer pow2 value, converting
    diving into shifts in the code. That's more preferable for Tegra30 that
    doesn't have hardware divider instructions because of older Cortex-A9 CPU.
    In a result boosting events are delayed by 4ms, which is not sensible in
    practice at all.

    Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
    Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
    ---
    drivers/devfreq/tegra30-devfreq.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
    index 8280f96f4cb9..3543fba74b52 100644
    --- a/drivers/devfreq/tegra30-devfreq.c
    +++ b/drivers/devfreq/tegra30-devfreq.c
    @@ -67,7 +67,7 @@
    * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128
    */
    #define ACTMON_AVERAGE_WINDOW_LOG2 6
    -#define ACTMON_SAMPLING_PERIOD 12 /* ms */
    +#define ACTMON_SAMPLING_PERIOD 16 /* ms */

    #define KHZ 1000

    --
    2.22.0
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