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SubjectRe: [PATCH 1/4][V3] spi: Add optional stall delay between cs_change transfers
On Mon, Jul 22, 2019 at 03:47:44PM +0300, Alexandru Ardelean wrote:
> Some devices like the ADIS16460 IMU require a longer period between
> transfers, i.e. between when the CS is de-asserted and re-asserted. The
> default value of 10us is not enough. This change makes the delay
> configurable for when the next CS change goes active, allowing the default
> to remain 10us is case it is unspecified.

For the third time:

| This looks like cs_change_delay.

> #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
> u8 bits_per_word;
> u8 word_delay_usecs;
> + u8 cs_change_delay;
> u16 delay_usecs;
> u32 speed_hz;
> u16 word_delay;

This patch doesn't apply and even if it did it won't compile because you
are trying to add a field with the same name as an existing one.
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