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SubjectRe: About threaded interrupt handler CPU affinity
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On 22/07/2019 15:41, Marc Zyngier wrote:
> Hi John,

Hi Marc,

>
> On 22/07/2019 15:14, John Garry wrote:
>> Hi Thomas,
>>
>> I have a question on commit cbf8699996a6 ("genirq: Let irq thread follow
>> the effective hard irq affinity"), if you could kindly check:
>>
>> Here we set the thread affinity to be the same as the hard interrupt
>> affinity. For an arm64 system with GIC ITS, this will be a single CPU,
>> the lowest in the interrupt affinity mask. So, in this case, effectively
>> the thread will be bound to a single CPU. I think APIC is the same for this.
>>
>> The commit message describes the problem that we solve here is that the
>> thread may become affine to a different CPU to the hard interrupt - does
>> it mean that the thread CPU mask could not cover that of the hard
>> interrupt? I couldn't follow the reason.
>
> Assume a 4 CPU system. If the interrupt affinity is on CPU0-1, you could
> end up with the effective interrupt affinity on CPU0 (which would be
> typical of the ITS), and the thread running on CPU1. Not great.

Sure, not great. But the thread can possibly still run on CPU0.

>
> The change you mentions ensures that the thread affinity is strictly
> equal to the *effective affinity* of the interrupt (or at least that's
> the way I read it).
>
>> We have experimented with fixing the thread mask to be the same as the
>> interrupt mask (we're using managed interrupts), like before, and get a
>> significant performance boost at high IO datarates on our storage
>> controller - like ~11%.
>
> My understanding is that this patch does exactly that. Does it result in
> a regression?

Not in the strictest sense for us, I don't know about others. Currently
we use tasklets, and we find that the CPUs servicing the interrupts (and
hence tasklets) are heavily loaded. We experience the same for when
experimenting with threaded interrupt handlers - which would be as expected.

But, when we make the change as mentioned, our IOPS goes from ~3M -> 3.4M.

I would say that a. CPU0 not always having to deal with the interrupt
handler+threaded part b. less context switching from a. would be factors
in this.

Thanks,
John


>
> Thanks,
>
> M.
>


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