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    Subject[PATCH v7 1/4] mtd: spi-nor: add support for is25wp256
    Date
    Update spi_nor_id table for is25wp256 (32MB) device from ISSI,
    present on HiFive Unleashed dev board (Rev: A00).

    Set method to enable quad mode for ISSI device in flash parameters
    table.

    Based on code originally written by Wesley Terpstra <wesley@sifive.com>
    and/or Palmer Dabbelt <palmer@sifive.com>
    https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b

    Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
    ---
    drivers/mtd/spi-nor/spi-nor.c | 9 ++++++++-
    include/linux/mtd/spi-nor.h | 1 +
    2 files changed, 9 insertions(+), 1 deletion(-)

    diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
    index e3a28c0..971f0f3 100644
    --- a/drivers/mtd/spi-nor/spi-nor.c
    +++ b/drivers/mtd/spi-nor/spi-nor.c
    @@ -1857,7 +1857,10 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
    { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
    -
    + { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 1024,
    + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
    + SPI_NOR_4B_OPCODES)
    + },
    /* Macronix */
    { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
    { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
    @@ -3687,6 +3690,10 @@ static int spi_nor_init_params(struct spi_nor *nor,
    case SNOR_MFR_ST:
    case SNOR_MFR_MICRON:
    break;
    + case SNOR_MFR_ISSI:
    + params->quad_enable = macronix_quad_enable;
    + break;
    +

    default:
    /* Kept only for backward compatibility purpose. */
    diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
    index b3d360b..b0e42b3 100644
    --- a/include/linux/mtd/spi-nor.h
    +++ b/include/linux/mtd/spi-nor.h
    @@ -21,6 +21,7 @@
    #define SNOR_MFR_INTEL CFI_MFR_INTEL
    #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */
    #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */
    +#define SNOR_MFR_ISSI 0x9d /* ISSI */
    #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
    #define SNOR_MFR_SPANSION CFI_MFR_AMD
    #define SNOR_MFR_SST CFI_MFR_SST
    --
    1.9.1
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