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    Subject[PATCH AUTOSEL 5.1 017/141] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE
    Date
    From: Tiecheng Zhou <Tiecheng.Zhou@amd.com>

    [ Upstream commit fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 ]

    it requires to initialize HDP_NONSURFACE_BASE, so as to avoid
    using the value left by a previous VM under sriov scenario.

    v2: it should not hurt baremetal, generalize it for both sriov
    and baremetal

    Signed-off-by: Emily Deng <Emily.Deng@amd.com>
    Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
    1 file changed, 3 insertions(+)

    diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    index 1611bef19a2c..c0446af00cdd 100644
    --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    @@ -1135,6 +1135,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
    tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
    WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);

    + WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
    + WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
    +
    /* After HDP is initialized, flush HDP.*/
    adev->nbio_funcs->hdp_flush(adev, NULL);

    --
    2.20.1
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