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SubjectRe: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
Date
Thanks Paul

Paul and James could you test this final solution(at least for 5.2)?
Please revert the hack patch and apply this one.

Thanks


On Mon, 2019-07-15 at 23:34 +0200, Paul Bolle wrote:
> Hi Jose,
>
> Souza, Jose schreef op ma 15-07-2019 om 21:03 [+0000]:
> > So the issue did not happened again with the patch applied?
>
> Not in the three days that I've been running 5.2 kernels with the
> hack applied
> (so that should be about twelve hours of proper uptime).
>
> > If you still have the kernel 5.1 installed could you share your
> > /sys/kernel/debug/dri/0/i915_edp_psr_status with the older kernel?
> > We want to check if training values changed between kernel
> > versions.
>
> Sure. On 5.1.17 I get:
> Sink support: yes [0x01]
> PSR mode: PSR1 enabled
> Source PSR ctl: enabled [0x81f00626]
> Source PSR status: IDLE [0x040b0001]
> Busy frontbuffer bits: 0x00000000
>
> And, in case you need it, on 5.2.1+hack I get:
> Sink support: yes [0x01]
> PSR mode: PSR1 enabled
> Source PSR ctl: enabled [0x81f00626]
> Source PSR status: IDLE [0x04030006]
> Busy frontbuffer bits: 0x00000000
>
> Hope this helps,
>
>
> Paul
>
From 5d4fce9889e25828ee35481a09929e8ee616c933 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Tue, 16 Jul 2019 09:26:08 -0700
Subject: [PATCH] Revert "drm/i915/vbt: Parse and use the new field with PSR2
TP2/3 wakeup time"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch is causing PSR_CTL_TP2_TP3 to be set to
PSR_TP2_TP3_TIME_0us while VBT have a different value causing screen
freezing after exiting PSR.

For now lets just revert it and later I will bring it back fixed.

This reverts commit 88a0d9606aff09d2b1c5dbe95a9df9dac44e79b6.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_bios.c | 25 -------------------------
drivers/gpu/drm/i915/intel_psr.c | 8 ++++----
drivers/gpu/drm/i915/intel_vbt_defs.h | 3 ---
4 files changed, 4 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 066fd2a12851..d37262aa16ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1013,7 +1013,6 @@ struct intel_vbt_data {
enum psr_lines_to_wait lines_to_wait;
int tp1_wakeup_time_us;
int tp2_tp3_wakeup_time_us;
- int psr2_tp2_tp3_wakeup_time_us;
} psr;

struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1dc8d03ff127..455cc07392af 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -760,31 +760,6 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
}
-
- if (bdb->version >= 226) {
- u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
-
- wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
- switch (wakeup_time) {
- case 0:
- wakeup_time = 500;
- break;
- case 1:
- wakeup_time = 100;
- break;
- case 3:
- wakeup_time = 50;
- break;
- default:
- case 2:
- wakeup_time = 2500;
- break;
- }
- dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
- } else {
- /* Reusing PSR1 wakeup time for PSR2 in older VBTs */
- dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;
- }
}

static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 963663ba0edf..3926f4bf05f6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -523,12 +523,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)

val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);

- if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
- dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
+ if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+ dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
val |= EDP_PSR2_TP2_TIME_50us;
- else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR2_TP2_TIME_100us;
- else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
+ else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR2_TP2_TIME_500us;
else
val |= EDP_PSR2_TP2_TIME_2500us;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index fdbbb9a53804..bf3662ad5fed 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -772,9 +772,6 @@ struct psr_table {
/* TP wake up time in multiple of 100 */
u16 tp1_wakeup_time;
u16 tp2_tp3_wakeup_time;
-
- /* PSR2 TP2/TP3 wakeup time for 16 panels */
- u32 psr2_tp2_tp3_wakeup_time;
} __packed;

struct bdb_psr {
--
2.22.0
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