lkml.org 
[lkml]   [2019]   [Jul]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH AUTOSEL 5.1 090/219] x86/cpufeatures: Add FDP_EXCPTN_ONLY and ZERO_FCS_FDS
    Date
    From: Aaron Lewis <aaronlewis@google.com>

    [ Upstream commit cbb99c0f588737ec98c333558922ce47e9a95827 ]

    Add the CPUID enumeration for Intel's de-feature bits to accommodate
    passing these de-features through to kvm guests.

    These de-features are (from SDM vol 1, section 8.1.8):
    - X86_FEATURE_FDP_EXCPTN_ONLY: If CPUID.(EAX=07H,ECX=0H):EBX[bit 6] = 1, the
    data pointer (FDP) is updated only for the x87 non-control instructions that
    incur unmasked x87 exceptions.
    - X86_FEATURE_ZERO_FCS_FDS: If CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 1, the
    processor deprecates FCS and FDS; it saves each as 0000H.

    Signed-off-by: Aaron Lewis <aaronlewis@google.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Reviewed-by: Jim Mattson <jmattson@google.com>
    Cc: Fenghua Yu <fenghua.yu@intel.com>
    Cc: Frederic Weisbecker <frederic@kernel.org>
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
    Cc: marcorr@google.com
    Cc: Peter Feiner <pfeiner@google.com>
    Cc: pshier@google.com
    Cc: Robert Hoo <robert.hu@linux.intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Thomas Lendacky <Thomas.Lendacky@amd.com>
    Cc: x86-ml <x86@kernel.org>
    Link: https://lkml.kernel.org/r/20190605220252.103406-1-aaronlewis@google.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/x86/include/asm/cpufeatures.h | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    index 75f27ee2c263..1017b9c7dfe0 100644
    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -239,12 +239,14 @@
    #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
    #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
    #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
    +#define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */
    #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
    #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
    #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
    #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
    #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
    #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
    +#define X86_FEATURE_ZERO_FCS_FDS ( 9*32+13) /* "" Zero out FPU CS and FPU DS */
    #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
    #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
    #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
    --
    2.20.1
    \
     
     \ /
      Last update: 2019-07-15 17:15    [W:4.044 / U:0.912 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site