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    Subject[PATCH 5.1 048/138] riscv: Fix udelay in RV32.
    Date
    [ Upstream commit d0e1f2110a5eeb6e410b2dd37d98bc5b30da7bc7 ]

    In RV32, udelay would delay the wrong cycle. When it shifts right
    "UDELAY_SHIFT" bits, it either delays 0 cycle or 1 cycle. It only works
    correctly in RV64. Because the 'ucycles' always needs to be 64 bits
    variable.

    Signed-off-by: Nick Hu <nickhu@andestech.com>
    Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
    [paul.walmsley@sifive.com: fixed minor spelling error]
    Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/riscv/lib/delay.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/riscv/lib/delay.c b/arch/riscv/lib/delay.c
    index dce8ae24c6d3..ee6853c1e341 100644
    --- a/arch/riscv/lib/delay.c
    +++ b/arch/riscv/lib/delay.c
    @@ -88,7 +88,7 @@ EXPORT_SYMBOL(__delay);

    void udelay(unsigned long usecs)
    {
    - unsigned long ucycles = usecs * lpj_fine * UDELAY_MULT;
    + u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT;

    if (unlikely(usecs > MAX_UDELAY_US)) {
    __delay((u64)usecs * riscv_timebase / 1000000ULL);
    --
    2.20.1


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