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    Subject[PATCH v4 13/22] iommu/vt-d: Enlightened PASID allocation
    Date
    From: Lu Baolu <baolu.lu@linux.intel.com>

    If Intel IOMMU runs in caching mode, a.k.a. virtual IOMMU, the
    IOMMU driver should rely on the emulation software to allocate
    and free PASID IDs. The Intel vt-d spec revision 3.0 defines a
    register set to support this. This includes a capability register,
    a virtual command register and a virtual response register. Refer
    to section 10.4.42, 10.4.43, 10.4.44 for more information.

    This patch adds the enlightened PASID allocation/free interfaces
    via the virtual command register.

    Cc: Ashok Raj <ashok.raj@intel.com>
    Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
    Cc: Kevin Tian <kevin.tian@intel.com>
    Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
    Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
    Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
    ---
    drivers/iommu/intel-pasid.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
    drivers/iommu/intel-pasid.h | 13 +++++++-
    include/linux/intel-iommu.h | 2 ++
    3 files changed, 90 insertions(+), 1 deletion(-)

    diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
    index 2fefeaf..69fddd3 100644
    --- a/drivers/iommu/intel-pasid.c
    +++ b/drivers/iommu/intel-pasid.c
    @@ -63,6 +63,82 @@ void *intel_pasid_lookup_id(int pasid)
    return p;
    }

    +int vcmd_alloc_pasid(struct intel_iommu *iommu, unsigned int *pasid)
    +{
    + u64 res;
    + u64 cap;
    + u8 status_code;
    + unsigned long flags;
    + int ret = 0;
    +
    + if (!ecap_vcs(iommu->ecap)) {
    + pr_warn("IOMMU: %s: Hardware doesn't support virtual command\n",
    + iommu->name);
    + return -ENODEV;
    + }
    +
    + cap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
    + if (!(cap & DMA_VCS_PAS)) {
    + pr_warn("IOMMU: %s: Emulation software doesn't support PASID allocation\n",
    + iommu->name);
    + return -ENODEV;
    + }
    +
    + raw_spin_lock_irqsave(&iommu->register_lock, flags);
    + dmar_writeq(iommu->reg + DMAR_VCMD_REG, VCMD_CMD_ALLOC);
    + IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq,
    + !(res & VCMD_VRSP_IP), res);
    + raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
    +
    + status_code = VCMD_VRSP_SC(res);
    + switch (status_code) {
    + case VCMD_VRSP_SC_SUCCESS:
    + *pasid = VCMD_VRSP_RESULT(res);
    + break;
    + case VCMD_VRSP_SC_NO_PASID_AVAIL:
    + pr_info("IOMMU: %s: No PASID available\n", iommu->name);
    + ret = -ENOMEM;
    + break;
    + default:
    + ret = -ENODEV;
    + pr_warn("IOMMU: %s: Unkonwn error code %d\n",
    + iommu->name, status_code);
    + }
    +
    + return ret;
    +}
    +
    +void vcmd_free_pasid(struct intel_iommu *iommu, unsigned int pasid)
    +{
    + u64 res;
    + u8 status_code;
    + unsigned long flags;
    +
    + if (!ecap_vcs(iommu->ecap)) {
    + pr_warn("IOMMU: %s: Hardware doesn't support virtual command\n",
    + iommu->name);
    + return;
    + }
    +
    + raw_spin_lock_irqsave(&iommu->register_lock, flags);
    + dmar_writeq(iommu->reg + DMAR_VCMD_REG, (pasid << 8) | VCMD_CMD_FREE);
    + IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq,
    + !(res & VCMD_VRSP_IP), res);
    + raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
    +
    + status_code = VCMD_VRSP_SC(res);
    + switch (status_code) {
    + case VCMD_VRSP_SC_SUCCESS:
    + break;
    + case VCMD_VRSP_SC_INVALID_PASID:
    + pr_info("IOMMU: %s: Invalid PASID\n", iommu->name);
    + break;
    + default:
    + pr_warn("IOMMU: %s: Unkonwn error code %d\n",
    + iommu->name, status_code);
    + }
    +}
    +
    /*
    * Per device pasid table management:
    */
    diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h
    index 23537b3..4b26ab5 100644
    --- a/drivers/iommu/intel-pasid.h
    +++ b/drivers/iommu/intel-pasid.h
    @@ -19,6 +19,16 @@
    #define PASID_PDE_SHIFT 6
    #define MAX_NR_PASID_BITS 20

    +/* Virtual command interface for enlightened pasid management. */
    +#define VCMD_CMD_ALLOC 0x1
    +#define VCMD_CMD_FREE 0x2
    +#define VCMD_VRSP_IP 0x1
    +#define VCMD_VRSP_SC(e) (((e) >> 1) & 0x3)
    +#define VCMD_VRSP_SC_SUCCESS 0
    +#define VCMD_VRSP_SC_NO_PASID_AVAIL 1
    +#define VCMD_VRSP_SC_INVALID_PASID 1
    +#define VCMD_VRSP_RESULT(e) (((e) >> 8) & 0xfffff)
    +
    /*
    * Domain ID reserved for pasid entries programmed for first-level
    * only and pass-through transfer modes.
    @@ -69,5 +79,6 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
    struct device *dev, int pasid);
    void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
    struct device *dev, int pasid);
    -
    +int vcmd_alloc_pasid(struct intel_iommu *iommu, unsigned int *pasid);
    +void vcmd_free_pasid(struct intel_iommu *iommu, unsigned int pasid);
    #endif /* __INTEL_PASID_H */
    diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
    index 6925a18..bff907b 100644
    --- a/include/linux/intel-iommu.h
    +++ b/include/linux/intel-iommu.h
    @@ -173,6 +173,7 @@
    #define ecap_smpwc(e) (((e) >> 48) & 0x1)
    #define ecap_flts(e) (((e) >> 47) & 0x1)
    #define ecap_slts(e) (((e) >> 46) & 0x1)
    +#define ecap_vcs(e) (((e) >> 44) & 0x1)
    #define ecap_smts(e) (((e) >> 43) & 0x1)
    #define ecap_dit(e) ((e >> 41) & 0x1)
    #define ecap_pasid(e) ((e >> 40) & 0x1)
    @@ -289,6 +290,7 @@

    /* PRS_REG */
    #define DMA_PRS_PPR ((u32)1)
    +#define DMA_VCS_PAS ((u64)1)

    #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
    do { \
    --
    2.7.4
    \
     
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