lkml.org 
[lkml]   [2019]   [Jun]   [7]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH v7 05/27] x86/fpu/xstate: Add XSAVES system states for shadow stack
From
Date
On Fri, 2019-06-07 at 09:07 +0200, Peter Zijlstra wrote:
> On Thu, Jun 06, 2019 at 01:06:24PM -0700, Yu-cheng Yu wrote:
> > Intel Control-flow Enforcement Technology (CET) introduces the
> > following MSRs.
> >
> > MSR_IA32_U_CET (user-mode CET settings),
> > MSR_IA32_PL3_SSP (user-mode shadow stack),
> > MSR_IA32_PL0_SSP (kernel-mode shadow stack),
> > MSR_IA32_PL1_SSP (Privilege Level 1 shadow stack),
> > MSR_IA32_PL2_SSP (Privilege Level 2 shadow stack).
> >
> > Introduce them into XSAVES system states.
> >
> > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
> > ---
> > arch/x86/include/asm/fpu/types.h | 22 +++++++++++++++++++++
> > arch/x86/include/asm/fpu/xstate.h | 4 +++-
> > arch/x86/include/uapi/asm/processor-flags.h | 2 ++
> > arch/x86/kernel/fpu/xstate.c | 10 ++++++++++
> > 4 files changed, 37 insertions(+), 1 deletion(-)
>
> And yet, no changes to msr-index.h !?

You are right. I will move msr-index.h changes to here.

Yu-cheng

\
 
 \ /
  Last update: 2019-06-07 18:23    [W:0.074 / U:7.268 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site