Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH 1/5] clk: ingenic: Add support for divider tables | Date | Fri, 07 Jun 2019 14:03:45 -0700 |
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Quoting Paul Cercueil (2019-05-02 14:24:58) > Some clocks provided on Ingenic SoCs have dividers, whose hardware value > as written in the register cannot be expressed as an affine function > to the actual divider value. > > For instance, for the CPU clock on the JZ4770, the dividers are coded as > follows: > > ------------------
Applied to clk-next
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