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SubjectRe: [PATCH V2 3/4] arm64/mm: Consolidate page fault information capture
On Thu, Jun 06, 2019 at 10:38:11AM +0100, Mark Rutland wrote:
> On Tue, Jun 04, 2019 at 03:42:09PM +0100, Catalin Marinas wrote:
> > On Mon, Jun 03, 2019 at 12:11:24PM +0530, Anshuman Khandual wrote:
> > > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
> > > index da02678..4bb65f3 100644
> > > --- a/arch/arm64/mm/fault.c
> > > +++ b/arch/arm64/mm/fault.c
> > > @@ -435,6 +435,14 @@ static bool is_el0_instruction_abort(unsigned int esr)
> > > return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW;
> > > }
> > >
> > > +/*
> > > + * This is applicable only for EL0 write aborts.
> > > + */
> > > +static bool is_el0_write_abort(unsigned int esr)
> > > +{
> > > + return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM);
> > > +}
> >
> > What makes this EL0 only?
>
> It returns false for EL1 faults caused by DC IVAC, where write
> permission is required. EL0 can only issue maintenance that requires
> read permission.
>
> For whatever reason, the architecture says that WnR is always 1b1, even
> if read permission was sufficient.
>
> How about:
>
> /*
> * Note: not valid for EL1 DC IVAC, but we never use that such that it
> * should fault.
> */

For completeness, I'd add "... should fault. EL0 cannot issue DC IVAC
(undef)." or something like that.

Looks fine otherwise.

--
Catalin

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