Messages in this thread | | | Date | Tue, 4 Jun 2019 15:37:00 -0700 | From | Bjorn Andersson <> | Subject | Re: [PATCH] arm64: dts: sdm845: Add iommus property to qup1 |
| |
On Tue 04 Jun 15:29 PDT 2019, Stephen Boyd wrote:
> The SMMU that sits in front of the QUP needs to be programmed properly > so that the i2c geni driver can allocate DMA descriptors. Failure to do > this leads to faults when using devices such as an i2c touchscreen where > the transaction is larger than 32 bytes and we use a DMA buffer. >
I'm pretty sure I've run into this problem, but before we marked the smmu bypass_disable and as such didn't get the fault, thanks.
> arm-smmu 15000000.iommu: Unexpected global fault, this could be serious > arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000 > > Add the right SID and mask so this works. > > Cc: Sibi Sankar <sibis@codeaurora.org> > Signed-off-by: Stephen Boyd <swboyd@chromium.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index fcb93300ca62..2e57e861e17c 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -900,6 +900,7 @@ > #address-cells = <2>; > #size-cells = <2>; > ranges; > + iommus = <&apps_smmu 0x6c0 0x3>;
According to the docs this stream belongs to TZ, the HLOS stream should be 0x6c3.
Regards, Bjorn
> status = "disabled"; > > i2c8: i2c@a80000 { > -- > Sent by a computer through tubes >
| |