lkml.org 
[lkml]   [2019]   [Jun]   [25]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH] clk: socfpga: stratix10: add additional clocks needed for the NAND IP
Date
Quoting Dinh Nguyen (2019-06-24 14:47:10)
> The nand_clk is actually called the nand_x_clk and the parent is the
> l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
> nand_x_clk and has a fixed divider of 4. The same is true for the
> nand_ecc_clk.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---

Applied to clk-next

\
 
 \ /
  Last update: 2019-06-25 23:37    [W:0.028 / U:31.564 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site