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SubjectRe: [PATCH] clk: socfpga: stratix10: add additional clocks needed for the NAND IP
Quoting Dinh Nguyen (2019-06-24 14:47:10)
> The nand_clk is actually called the nand_x_clk and the parent is the
> l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
> nand_x_clk and has a fixed divider of 4. The same is true for the
> nand_ecc_clk.
> Signed-off-by: Dinh Nguyen <>
> ---

Applied to clk-next

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