Messages in this thread | | | From | Heiko Stuebner <> | Subject | Re: [PATCH 1/2] clk: rockchip: add a type from SGRF-controlled gate clocks | Date | Fri, 14 Jun 2019 18:57:37 +0200 |
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Am Donnerstag, 6. Juni 2019, 11:09:33 CEST schrieb Heiko Stuebner: > Some clk gates on Rockchip SoCs are part of the SGRF (secure general > register files) and thus only controllable from secure mode, with the > most prominent example being the watchdog. > > In most cases we still want to define this as a real clock though, > to have complete clock tree and not reference the generic base-clock > from the devicetree. > > So far we've just defined this as factor-1-1 clocks in the clock init, > so define a special clock-type for it so that this definition can be > part of the general tree-definition and save some boilerplate code. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
applied both for 5.3
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