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    Subject[PATCH V10 03/15] PCI: dwc: Perform dbi regs write lock towards the end
    Date
    Remove multiple write enable and disable sequences of dbi registers as
    Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
    DBI write-lock enable bit thereby not allowing any further writes to BAR-0
    register in config space to take place. Hence enabling write permission at
    the start of function and disabling the same only towards the end.

    Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
    Reviewed-by: Thierry Reding <treding@nvidia.com>
    ---
    Changes since [v9]:
    * None

    Changes since [v8]:
    * None

    Changes since [v7]:
    * None

    Changes since [v6]:
    * None

    Changes since [v5]:
    * Moved write enable to the beginning of the API and write disable to the end

    Changes since [v4]:
    * None

    Changes since [v3]:
    * None

    Changes since [v2]:
    * None

    Changes since [v1]:
    * None

    drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
    1 file changed, 8 insertions(+), 6 deletions(-)

    diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
    index f93252d0da5b..d3156446ff27 100644
    --- a/drivers/pci/controller/dwc/pcie-designware-host.c
    +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
    @@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
    u32 val, ctrl, num_ctrls;
    struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

    + /*
    + * Enable DBI read-only registers for writing/updating configuration.
    + * Write permission gets disabled towards the end of this function.
    + */
    + dw_pcie_dbi_ro_wr_en(pci);
    +
    dw_pcie_setup(pci);

    if (!pp->ops->msi_host_init) {
    @@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
    dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);

    /* Setup interrupt pins */
    - dw_pcie_dbi_ro_wr_en(pci);
    val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
    val &= 0xffff00ff;
    val |= 0x00000100;
    dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
    - dw_pcie_dbi_ro_wr_dis(pci);

    /* Setup bus numbers */
    val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
    @@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)

    dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);

    - /* Enable write permission for the DBI read-only register */
    - dw_pcie_dbi_ro_wr_en(pci);
    /* Program correct class for RC */
    dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
    - /* Better disable write permission right after the update */
    - dw_pcie_dbi_ro_wr_dis(pci);

    dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
    val |= PORT_LOGIC_SPEED_CHANGE;
    dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
    +
    + dw_pcie_dbi_ro_wr_dis(pci);
    }
    EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
    --
    2.17.1
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