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SubjectRe: [PATCH v8 26/29] vfio-pci: Register an iommu fault handler
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On 10/06/2019 22:31, Jacob Pan wrote:
> On Mon, 10 Jun 2019 13:45:02 +0100
> Jean-Philippe Brucker <jean-philippe.brucker@arm.com> wrote:
>
>> On 07/06/2019 18:43, Jacob Pan wrote:
>>>>> So it seems we agree on the following:
>>>>> - iommu_unregister_device_fault_handler() will never fail
>>>>> - iommu driver cleans up all pending faults when handler is
>>>>> unregistered
>>>>> - assume device driver or guest not sending more page response
>>>>> _after_ handler is unregistered.
>>>>> - system will tolerate rare spurious response
>>>>>
>>>>> Sounds right?
>>>>
>>>> Yes, I'll add that to the fault series
>>> Hold on a second please, I think we need more clarifications. Ashok
>>> pointed out to me that the spurious response can be harmful to other
>>> devices when it comes to mdev, where PRQ group id is not per PASID,
>>> device may reuse the group number and receiving spurious page
>>> response can confuse the entire PF.
>>
>> I don't understand how mdev differs from the non-mdev situation (but I
>> also still don't fully get how mdev+PASID will be implemented). Is the
>> following the case you're worried about?
>>
>> M#: mdev #
>>
>> # Dev Host mdev drv VFIO/QEMU Guest
>> ====================================================================
>> 1 <- reg(handler)
>> 2 PR1 G1 P1 -> M1 PR1 G1 inject -> M1 PR1 G1
>> 3 <- unreg(handler)
>> 4 <- PS1 G1 P1 (F) |
>> 5 unreg(handler)
>> 6 <- reg(handler)
>> 7 PR2 G1 P1 -> M2 PR2 G1 inject -> M2 PR2 G1
>> 8 <- M1 PS1 G1
>> 9 accept ?? <- PS1 G1 P1
>> 10 <- M2 PS2 G1
>> 11 accept <- PS2 G1 P1
>>
> Not really. I am not worried about PASID reuse or unbind. Just within
> the same PASID bind lifetime of a single mdev, back to back
> register/unregister fault handler.
> After Step 4, device will think G1 is done. Device could reuse G1 for
> the next PR, if we accept PS1 in step 9, device will terminate G1 before
> the real G1 PS arrives in Step 11. The real G1 PS might have a
> different response code. Then we just drop the PS in Step 11?

Yes, I think we do. Two possibilities:

* G1 is reused at step 7 for the same PASID context, which means that it
is for the same mdev. The problem is then identical to the non-mdev
case, new page faults and old page response may cross:

# Dev Host mdev drv VFIO/QEMU Guest
====================================================================
7 PR2 G1 P1 --.
8 \ .------------- M1 PS1 G1
9 '-----> PR2 G1 P1 -> / inject --> M1 PR2 G1
10 accept <--- PS1 G1 P1 <--'
11 reject <--- PS2 G1 P1 <------------------ M1 PS2 G1

And the incorrect page response is returned to the guest. However it
affects a single mdev/guest context, it doesn't affect other mdevs.

* Or G1 is reused at step 7 for a different PASID. At step 10 the fault
handler rejects the page response because the PASID is different, and
step 11 is accepted.


>>> Having spurious page response is also not
>>> abiding the PCIe spec. exactly.
>>
>> We are following the PCI spec though, in that we don't send page
>> responses for PRGIs that aren't in flight.
>>
> You are right, the worst case of the spurious PS is to terminate the
> group prematurely. Need to know the scope of the HW damage in case of mdev
> where group IDs can be shared among mdevs belong to the same PF.

But from the IOMMU fault API point of view, the full page request is
identified by both PRGI and PASID. Given that each mdev has its own set
of PASIDs, it should be easy to isolate page responses per mdev.

Thanks,
Jean

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