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    Subject[PATCH v2 19/25] clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
    Date
    From: Chen-Yu Tsai <wens@csie.org>

    With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
    macros, we can reference parents locally via pointers to struct clk_hw
    or DT clock-names.

    Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
    _FW_NAME variant based on whether the parent clock is internal or
    external to the CCU.

    Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
    Signed-off-by: Chen-Yu Tsai <wens@csie.org>
    ---
    drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 29 ++++++++++++++++--------
    1 file changed, 19 insertions(+), 10 deletions(-)

    diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
    index e748b8a6f3c5..f6b776ca8e49 100644
    --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
    +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
    @@ -374,16 +374,25 @@ static struct ccu_common *suniv_ccu_clks[] = {
    &avs_clk.common,
    };

    -static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
    - "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
    -static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
    - "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
    -static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
    - "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
    -static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
    - "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
    -static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
    - "pll-video", 1, 2, 0);
    +static const struct clk_hw *clk_parent_pll_audio[] = {
    + &pll_audio_base_clk.common.hw
    +};
    +
    +static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
    + clk_parent_pll_audio
    + 4, 1, CLK_SET_RATE_PARENT);
    +static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
    + clk_parent_pll_audio
    + 2, 1, CLK_SET_RATE_PARENT);
    +static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
    + clk_parent_pll_audio
    + 1, 1, CLK_SET_RATE_PARENT);
    +static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
    + clk_parent_pll_audio
    + 1, 2, CLK_SET_RATE_PARENT);
    +static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
    + &pll_video0_clk.common.hw,
    + 1, 2, 0);

    static struct clk_hw_onecell_data suniv_hw_clks = {
    .hws = {
    --
    2.20.1
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