Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH] pinctrl: qcom: Clear status bit on irq_unmask | Date | Mon, 10 Jun 2019 07:51:32 -0700 |
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Quoting Linus Walleij (2019-06-07 14:08:10) > On Fri, May 31, 2019 at 8:52 AM Tengfei Fan <tengfeif@codeaurora.org> wrote: > > > The gpio interrupt status bit is getting set after the > > irq is disabled and causing an immediate interrupt after > > enablling the irq, so clear status bit on irq_unmask. > > > > Signed-off-by: Tengfei Fan <tengfeif@codeaurora.org> > > This looks pretty serious, can one of the Qcom maintainers ACK > this? > > Should it be sent to fixes and even stable? > > Fixes: tag? >
How is the interrupt status bit getting set after the irq is disabled? It looks like this is a level type interrupt? I thought that after commit b55326dc969e ("pinctrl: msm: Really mask level interrupts to prevent latching") this wouldn't be a problem. Am I wrong, or is qcom just clearing out patches on drivers and this is the last one that needs to be upstreamed?
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