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    Subject[PATCH AUTOSEL 4.14 55/95] drm/i915: Downgrade Gen9 Plane WM latency error
    Date
    From: Chris Wilson <chris@chris-wilson.co.uk>

    [ Upstream commit 86c1c87d0e6241cbe35bd52badfc84b154e1b959 ]

    According to intel_read_wm_latency() it is perfectly legal for one WM
    and all subsequent levels to be 0 (and the deeper powersaving states
    disabled), so don't shout *ERROR*, over and over again.

    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
    Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
    Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20180726161527.10516-1-chris@chris-wilson.co.uk
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    ---
    drivers/gpu/drm/i915/intel_pm.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
    index 96a5237741e0..cb377b003321 100644
    --- a/drivers/gpu/drm/i915/intel_pm.c
    +++ b/drivers/gpu/drm/i915/intel_pm.c
    @@ -2934,8 +2934,8 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
    unsigned int latency = wm[level];

    if (latency == 0) {
    - DRM_ERROR("%s WM%d latency not provided\n",
    - name, level);
    + DRM_DEBUG_KMS("%s WM%d latency not provided\n",
    + name, level);
    continue;
    }

    --
    2.20.1
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