Messages in this thread | | | Subject | Re: [PATCH v3 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT | From | Zhangshaokun <> | Date | Mon, 27 May 2019 15:14:50 +0800 |
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Hi Greg,
On 2019/5/27 14:08, Greg KH wrote: > On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote: >> cache_line_size is derived from CTR_EL0.CWG field and is called mostly >> for I/O device drivers. For HiSilicon certain plantform, like the >> Kunpeng920 server SoC, cache line sizes are different between L1/2 >> cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte, >> but CTR_EL0.CWG is misreporting using L1 cache line size. >> >> We shall correct the right value which is important for I/O performance. >> Let's update the cache line size if it is detected from DT or PPTT >> information. >> >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will.deacon@arm.com> >> Cc: Sudeep Holla <sudeep.holla@arm.com> >> Cc: Jeremy Linton <jeremy.linton@arm.com> >> Cc: Zhenfa Qiu <qiuzhenfa@hisilicon.com> >> Reported-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com> >> Suggested-by: Catalin Marinas <catalin.marinas@arm.com> >> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> >> --- >> arch/arm64/include/asm/cache.h | 6 +----- >> arch/arm64/kernel/cacheinfo.c | 11 +++++++++++ >> 2 files changed, 12 insertions(+), 5 deletions(-) >> >> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h >> index 926434f413fa..758af6340314 100644 >> --- a/arch/arm64/include/asm/cache.h >> +++ b/arch/arm64/include/asm/cache.h >> @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void) >> >> #define __read_mostly __attribute__((__section__(".data..read_mostly"))) >> >> -static inline int cache_line_size(void) >> -{ >> - u32 cwg = cache_type_cwg(); >> - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; >> -} >> +int cache_line_size(void); >> >> /* >> * Read the effective value of CTR_EL0. >> diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c >> index 0bf0a835122f..3d54b0024246 100644 >> --- a/arch/arm64/kernel/cacheinfo.c >> +++ b/arch/arm64/kernel/cacheinfo.c >> @@ -28,6 +28,17 @@ >> #define CLIDR_CTYPE(clidr, level) \ >> (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) >> >> +int cache_line_size(void) >> +{ >> + u32 cwg = cache_type_cwg(); >> + >> + if (coherency_max_size != 0) >> + return coherency_max_size; > > Ah, you use it here. >
Yeah, we check it here.
>> + >> + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; > > Shouldn't you set the variable if it is 0 here as well? >
As discussed this with Catalin, https://www.spinics.net/lists/arm-kernel/msg723848.html
I think it is unnecessary, if coherency_max_size is not detected from firmware, We will return the cpu core reporting value as the cache line size and coherency_max_size won't be used in other place.
>> +} >> +EXPORT_SYMBOL(cache_line_size); > > EXPORT_SYMBOL_GPL()? >
Ok.
Thanks, Shaokun
> thanks, > > greg k-h > > . >
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