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SubjectRe: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set in hardware
On Fri, May 17, 2019 at 03:46:07PM +0000, Ghannam, Yazen wrote:
> I think there are a couple of issues here.
> 1) The bank is being initialized without accounting for any quirks.

Almost. __mcheck_cpu_init_clear_banks() a little bit later corrects
that. I guess I can drop the

wrmsrl(msr_ops.status(i), 0);

in here because __mcheck_cpu_init_clear_banks() does that too.

Now, the

wrmsrl(msr_ops.ctl(i), -1)
rdmsrl(msr_ops.ctl(i), val);

method of throwing all 1s to see what sticks is what Intel wants, as
Tony said. Is that going to be a problem on AMD?

> 2) The bank is being initialized without having set up any handler or
> other appropriate setup.

I'm afraid you're going to have to explain this in more detail...


Good mailing practices for 400: avoid top-posting and trim the reply.

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