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SubjectRe: [PATCH 4/6] arm64: pmu: Add hook to handle pmu-related undefined instructions
On Fri, May 17, 2019 at 10:26:55AM +0200, Peter Zijlstra wrote:
> On Fri, May 17, 2019 at 09:04:20AM +0100, Mark Rutland wrote:
>
> > Remember that this is in an undefined (trap) handler.
> >
> > If userspace _attempts_ to write to the registers, the CPU will trap to the
> > kernel. The comment is perhaps misleading; when we "do nothing", the common
> > trap handling code will send a SIGILL to userspace.
> >
> > It would probably be better to say something like:
> >
> > /*
> > * If userspace is tries to read a counter that doesn't exist on this
> > * CPU, we emulate it as reading as zero. This happens if userspace is
> > * preempted between reading the idx and actually reading the counter,
> > * and the seqlock and idx have already changed, so it's as-if the
> > * counter has been reprogrammed with a different event.
>
> Might be good to mention that userspace will/should discard the value it
> reads, and therefore any value is good (including 0).
>
> > * We don't permit userspace to write to these registers, and will
> > * inject a SIGILL.
> > */
> >
> > There is one caveat: userspace can write to PMSELR without trapping, so we will
> > have to context-switch with the task. That only affects indirect addressing of
> > PMU registers, and doesn't have a functional effect on the behaviour of the
> > PMU, so that's benign from the PoV of perf.
>
> Sad though; ideally you'd state that indirect addressing is
> out-of-bounds and they get to keep the pieces. But I suspect you're
> right that people will do it anyway and complain once it comes apart.

I'm still not entirely convinced you need that context switching. If we
sched-out, the seqcount value will change, idem when we sched-in. So
under no circumstance (even if we stay on the same CPU), will the
seqcount match when we get back on.

So why preserve that register?

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