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    Subject[PATCH 4.4 186/266] x86/speculation: Simplify the CPU bug detection logic
    Date
    From: Dominik Brodowski <linux@dominikbrodowski.net>

    commit 8ecc4979b1bd9c94168e6fc92960033b7a951336 upstream.

    Only CPUs which speculate can speculate. Therefore, it seems prudent
    to test for cpu_no_speculation first and only then determine whether
    a specific speculating CPU is susceptible to store bypass speculation.
    This is underlined by all CPUs currently listed in cpu_no_speculation
    were present in cpu_no_spec_store_bypass as well.

    Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Cc: bp@suse.de
    Cc: konrad.wilk@oracle.com
    Link: https://lkml.kernel.org/r/20180522090539.GA24668@light.dominikbrodowski.net
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/x86/kernel/cpu/common.c | 22 +++++++---------------
    1 file changed, 7 insertions(+), 15 deletions(-)

    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -859,12 +859,8 @@ static const __initconst struct x86_cpu_
    {}
    };

    +/* Only list CPUs which speculate but are non susceptible to SSB */
    static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
    - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW },
    - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT },
    - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL },
    - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW },
    - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW },
    { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
    { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
    { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
    @@ -872,14 +868,10 @@ static const __initconst struct x86_cpu_
    { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
    { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
    { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
    - { X86_VENDOR_CENTAUR, 5, },
    - { X86_VENDOR_INTEL, 5, },
    - { X86_VENDOR_NSC, 5, },
    { X86_VENDOR_AMD, 0x12, },
    { X86_VENDOR_AMD, 0x11, },
    { X86_VENDOR_AMD, 0x10, },
    { X86_VENDOR_AMD, 0xf, },
    - { X86_VENDOR_ANY, 4, },
    {}
    };

    @@ -902,6 +894,12 @@ static void __init cpu_set_bug_bits(stru
    {
    u64 ia32_cap = 0;

    + if (x86_match_cpu(cpu_no_speculation))
    + return;
    +
    + setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
    + setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
    +
    if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
    rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);

    @@ -909,12 +907,6 @@ static void __init cpu_set_bug_bits(stru
    !(ia32_cap & ARCH_CAP_SSB_NO))
    setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);

    - if (x86_match_cpu(cpu_no_speculation))
    - return;
    -
    - setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
    - setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
    -
    if (ia32_cap & ARCH_CAP_IBRS_ALL)
    setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);


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