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SubjectRe: Hardware-accelerated video decoders used through a firmware instead of hardware registers
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Date
Hi,

On Sun, 2019-05-12 at 18:32 +0200, Paul Kocialkowski wrote:
[...]
> I would be curious to know what the situation is on the i.MX6 coda
> block, which also seems pretty obscure.

FWIW, I had started collecting things I learned about the BIT processor
in the CODA IP cores, mostly by looking at the firmware files
distributed by Freescale/NXP: https://github.com/pH5/coda-bits

It is a somewhat strange custom 16-bit DSP architecture. There is a
rudimentary start for a disassembler in there as well, but large parts
of the instruction set are still completely unknown, and I have no idea
how the address generator / DMA units or bitstream accelerators work.

I would be delighted if somebody would like to pick up analyzing the BIT
processor ISA further. I think it could be fruitful to start
systematically throwing instructions at it and see what happens, to
learn more. I haven't had much motivation to play with this, recently.

About the internal connections and available accelerator units, there is
a block diagram in the i.MX53 TRM, but I am not aware of any register
level description for any of these.

regards
Philipp

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