Messages in this thread | | | Subject | Re: [PATCH v3 02/16] iommu: Introduce cache_invalidate API | From | Jean-Philippe Brucker <> | Date | Mon, 13 May 2019 12:20:27 +0100 |
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Hi Eric,
On 13/05/2019 10:14, Auger Eric wrote: > I noticed my qemu integration was currently incorrectly using PASID > invalidation for ASID based invalidation (SMMUV3 Stage1 CMD_TLBI_NH_ASID > invalidation command). So I think we also need ARCHID invalidation. > Sorry for the late notice. >> >> +/* defines the granularity of the invalidation */ >> +enum iommu_inv_granularity { >> + IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */ > IOMMU_INV_GRANU_ARCHID, /* archid-selective invalidation */ >> + IOMMU_INV_GRANU_PASID, /* pasid-selective invalidation */
In terms of granularity, these values have the same meaning: invalidate the whole address space of a context. Then you can communicate two things using the same struct: * If ATS is enables an Arm host needs to invalidate all ATC entries using PASID. * If BTM isn't used by the guest, the host needs to invalidate all TLB entries using ARCHID.
Rather than introducing a new granule here, could we just add an archid field to the struct associated with IOMMU_INV_GRANU_PASID? Something like...
>> + IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */ >> + IOMMU_INVAL_GRANU_NR, /* number of invalidation granularities */ >> +}; >> + >> +/** >> + * Address Selective Invalidation Structure >> + * >> + * @flags indicates the granularity of the address-selective invalidation >> + * - if PASID bit is set, @pasid field is populated and the invalidation >> + * relates to cache entries tagged with this PASID and matching the >> + * address range. >> + * - if ARCHID bit is set, @archid is populated and the invalidation relates >> + * to cache entries tagged with this architecture specific id and matching >> + * the address range. >> + * - Both PASID and ARCHID can be set as they may tag different caches. >> + * - if neither PASID or ARCHID is set, global addr invalidation applies >> + * - LEAF flag indicates whether only the leaf PTE caching needs to be >> + * invalidated and other paging structure caches can be preserved. >> + * @pasid: process address space id >> + * @archid: architecture-specific id >> + * @addr: first stage/level input address >> + * @granule_size: page/block size of the mapping in bytes >> + * @nb_granules: number of contiguous granules to be invalidated >> + */ >> +struct iommu_inv_addr_info { >> +#define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0) >> +#define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1) >> +#define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2) >> + __u32 flags; >> + __u32 archid; >> + __u64 pasid; >> + __u64 addr; >> + __u64 granule_size; >> + __u64 nb_granules; >> +};
struct iommu_inv_pasid_info { #define IOMMU_INV_PASID_FLAGS_PASID (1 << 0) #define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1) __u32 flags; __u32 archid; __u64 pasid; };
>> + >> +/** >> + * First level/stage invalidation information >> + * @cache: bitfield that allows to select which caches to invalidate >> + * @granularity: defines the lowest granularity used for the invalidation: >> + * domain > pasid > addr >> + * >> + * Not all the combinations of cache/granularity make sense: >> + * >> + * type | DEV_IOTLB | IOTLB | PASID | >> + * granularity | | | cache | >> + * -------------+---------------+---------------+---------------+ >> + * DOMAIN | N/A | Y | Y | > * ARCHID | N/A | Y | N/A | > >> + * PASID | Y | Y | Y | >> + * ADDR | Y | Y | N/A | >> + * >> + * Invalidations by %IOMMU_INV_GRANU_ADDR use field @addr_info. > * Invalidations by %IOMMU_INV_GRANU_ARCHID use field @archid. >> + * Invalidations by %IOMMU_INV_GRANU_PASID use field @pasid. >> + * Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument. >> + * >> + * If multiple cache types are invalidated simultaneously, they all >> + * must support the used granularity. >> + */ >> +struct iommu_cache_invalidate_info { >> +#define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1 >> + __u32 version; >> +/* IOMMU paging structure cache */ >> +#define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */ >> +#define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */ >> +#define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */ >> +#define IOMMU_CACHE_TYPE_NR (3) >> + __u8 cache; >> + __u8 granularity; >> + __u8 padding[2]; >> + union { >> + __u64 pasid; > __u32 archid;
struct iommu_inv_pasid_info pasid_info;
Thanks, Jean
> > Thanks > > Eric >> + struct iommu_inv_addr_info addr_info; >> + }; >> +}; >> + >> + >> #endif /* _UAPI_IOMMU_H */ >>
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