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Subject[PATCH] x86/tsc: mark tsc reliable on CoffeeLake
Date
From: You-Sheng Yang <vicamo.yang@canonical.com>

On Intel CoffeeLake it's observed tsc is always marked unstable
unexpectedly after entering idle state Package C10(PC10), and then clock
source is switched to hpet. This patch marks tsc as reliable when CPUID
matches CoffeeLake.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=203183
Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
---
arch/x86/kernel/tsc.c | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index aab0c82e0a0d..2abbadc9cff0 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1161,6 +1161,16 @@ static void __init check_system_tsc_reliable(void)
#endif
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
tsc_clocksource_reliable = 1;
+
+ /*
+ * On Intel CoffeeLake, tsc may be marked unstable unexpectedly after
+ * entering PC10.
+ */
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+ (boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_MOBILE ||
+ boot_cpu_data.x86_model == INTEL_FAM6_KABYLAKE_DESKTOP) &&
+ boot_cpu_data.x86_stepping >= 0x0a)
+ tsc_clocksource_reliable = 1;
}

/*
--
2.20.1
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