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Subject[PATCH V2 00/16] Add Tegra194 PCIe support
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
to PCIe controller
This patch series
- Adds support for P2U PHY driver
- Adds support for PCIe host controller
- Adds device tree nodes each PCIe controllers
- Enables nodes applicable to p2972-0000 platform
- Adds helper APIs in Designware core driver to get capability regs offset
- Adds defines for new feature registers of PCIe spec revision 4
- Makes changes in DesignWare core driver to get Tegra194 PCIe working

Testing done on P2972-0000 platform
- Able to get PCIe link up with on-board Marvel eSATA controller
- Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
- Able to do data transfers with both SATA drives and NVMe cards

- Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194.
It is being worked on currently and hence Controller:5 (i.e. x8 slot) is
disabled in this patch series. A future patch series would enable this.
- This series is based on top of the following series
Jisheng's patches to add support to .remove() in Designware sub-system
My patches made on top of Jisheng's patches to export various symbols

Changes since [v1]:
* Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon
* Added more patches in v2 series

Vidya Sagar (16):
PCI: Add #defines for PCIe spec r4.0 features
PCI/PME: Export pcie_pme_disable_msi() API
PCI: Export pcie_bus_config symbol
PCI: dwc: Perform dbi regs write lock towards the end
PCI: dwc: Move config space capability search API
PCI: dwc: Add ext config space capability search API
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Add support to enable CDM register check
Documentation/devicetree: Add PCIe supports-clkreq property
dt-bindings: PCI: tegra: Add device tree support for T194
dt-bindings: PHY: P2U: Add Tegra 194 P2U block
arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
arm64: tegra: Enable PCIe slots in P2972-0000 board
phy: tegra: Add PCIe PIPE2UPHY support
PCI: tegra: Add Tegra194 PCIe support
arm64: Add Tegra194 PCIe driver to defconfig

.../devicetree/bindings/pci/designware-pcie.txt | 4 +
.../bindings/pci/nvidia,tegra194-pcie.txt | 181 ++
Documentation/devicetree/bindings/pci/pci.txt | 5 +
.../devicetree/bindings/phy/phy-tegra194-p2u.txt | 28 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 50 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 449 +++++
arch/arm64/configs/defconfig | 1 +
drivers/pci/controller/dwc/Kconfig | 11 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-designware-ep.c | 37 +-
drivers/pci/controller/dwc/pcie-designware-host.c | 3 -
drivers/pci/controller/dwc/pcie-designware.c | 81 +
drivers/pci/controller/dwc/pcie-designware.h | 12 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1760 ++++++++++++++++++++
drivers/pci/pci.c | 1 +
drivers/pci/pcie/pme.c | 6 +
drivers/pci/pcie/portdrv.h | 5 +-
drivers/phy/tegra/Kconfig | 7 +
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/pcie-p2u-tegra194.c | 120 ++
include/uapi/linux/pci_regs.h | 22 +-
22 files changed, 2743 insertions(+), 44 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c


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