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SubjectRe: [PATCH 2/2] clk: qoriq: add more PLL divider clocks support
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Quoting andy.tang@nxp.com (2019-04-22 02:15:09)
> From: Yuantian Tang <andy.tang@nxp.com>
>
> More PLL divider clocks are needed by clock consumer IP. So enlarge
> the PLL divider array to accommodate more divider clocks.
>
> Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
> ---

Applied to clk-next

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