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SubjectRE: [PATCH v8 13/15] x86/split_lock: Enable split lock detection by default
From: Thomas Gleixne]
> Sent: 25 April 2019 11:59
> On Thu, 25 Apr 2019, David Laight wrote:
> > From: Fenghua Yu
> > > Sent: 24 April 2019 20:33
> > > A split locked access locks bus and degrades overall memory access
> > > performance. When split lock detection feature is enumerated, enable
> > > the feature by default by writing 1 to bit 29 in MSR TEST_CTL to find
> > > any split lock issue.
> >
> > You can't enable this by default until ALL the known potentially
> > misaligned locked memory operations have been fixed.
> Errm? The result will be a WARN_ON() printed and no further damage.

ISTR something about sending SIGSEGV to userspace.

> It's not making anything worse than it is now. In fact we just should add a
> WARN_ON_ONCE(!aligned_to_long(p)) to all the xxx_bit() operations.
> so we catch them even when they do not trigger that #AC thingy.

That will explode the kernel code size.
In any case some of the items I found in a quick scan were bss/data
so the alignment will vary from build to build.

I also found some casts on the xxx_bit() functions in generic code.
I didn't look to see how badly wrong they go on BE systems.

While the x86 xxx_bit() functions could easily be changed to do
32bit accesses, the 'misaligned' operations will affect all
architectures - and may have different effects on others.

I'm not at all sure that 'compare and exchange' operations
are atomic on all cpus if the data is misaligned and crosses
a page boundary and either (or both) pages need faulting in
(or hit a TLB miss).


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