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Subject[RFC] Question about reset order for xhci controller and pci
Date
Hi,all

I've meet a problem about reset xhci and it may be caused by the
reset order of pci and xhci.
Using xhci-pci, when users send reset command in os(centos or red-hat os),
it would first reset PCI device by pci_reset_function. During this
process, it would disable BME(Bus Master Enable) and set BME=0, and
then enable it and set BME=1.
And then it comes to xhci reset process. First, it would send an
endpoint stop command in xhci_urb_dequeue. However, this stop ep command
fails to finish. The reason is that BME is set to 0 in former process and
xhci RUN/STOP changes to 0, and when BME is set to 1 again, RUN/STOP doesn't
recover to 1.
I've checked BME behavior in xhci spec, it shows that "If the BME bit is set to 0
when xHC is running, the xHC may treat this as a Host Controller Error, asserting
HCE(1) and immediately halt(R/S=0 and HCH=1). Recovery from this state will
require an HCRST." It seems that the stop ep command failure is reasonable.
Maybe I've missed something and please let me know.

linux version:5.0.0-rc3

Thanks,
Nianyao Tang

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