[lkml]   [2019]   [Apr]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH] riscv: Support non-coherency memory model
On Wed, Apr 24, 2019 at 12:45:56PM +0000, Gary Guo wrote:
> The RISC-V privileged spec is explicitly designed to allow the
> techniques described above (this is the sole purpose of MSTATUS.TVM). It
> might be as high performance as a hardware with H-extension, but is
> definitely a legit use case. In fact, it is vital for use cases like
> recursive virtualization.
> Also, I believe the PTE format of RISC-V is already frozen -- therefore
> it is impossible now to merge GLOBAL and USER bit, nor to replace RSW
> bit with another bit.

Yes, I do not think we can just repurpose a bit. Even using a currently
unused one would require some gymnastics.

That being said IFF we want to support non-coherent DMA (and I think we
do as people glue together their SOCs using shoestring and paper clips,
as already demonstrated by Andes and C-SKY in RISC-V space, and most
arm, mips and ppc SOCs) we need something like this flag. The current
RISC-V method that only allows M-mode to set up such attributes on
a small number or PMP regions just doesn't work well with the way how
Linux and most non-trivial OSes implement DMA memory allocations.

Note that I said well - in theory we can have a firmware provided
uncached pool - that is what Linux does on most nommu (that is without
pagetables) ports, but the fixed sized pool really does suck and will
make users very unhappy.

 \ /
  Last update: 2019-04-24 16:23    [W:0.089 / U:0.860 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site