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Subject[PATCH V5 00/12] perf: Add Icelake support (kernel only, except Topdown)
From: Kan Liang <>

To make the patch series easier to be reviewed and integrated, it is
condensed into a smaller set of patches, which only include essential
features of Icelake for kernel except new hardware Metrics counters for
Topdown events. The user space patch and Topdown support will be
submitted separately once the patch series is integrated.
(Please let me know if the Topdown/user space patches are still
expected to be included in this series)

The patch series intends to add Icelake support (except Topdown) for
Linux perf.

PATCH 1: Patch to fix wrong PEBS_REGS for large PEBS
PATCH 2-12: Kernel patches to support Icelake.
- 2-6: Support adaptive PEBS feature
- 7-8: Enable core support with some new features, e.g. 8 generic
counters, new event constraints, a new fixed counter.
- 9-12: Enable cstate, rapl, msr and uncore support on Icelake

Changes since V4:
- Separate the changes. Topdown support and user space patches will be
submitted separately.
- A patch to fix wrong PEBS_REGS for large PEBS
- Rename has_xmm_regs to pebs_no_xmm_regs
Add PEBS_XMM_REGS for XMM registers
Refine the extra check in x86_pmu_hw_config()

Changes since V3:
- Keep the old names for GPRs. Rename PERF_REG_X86_MAX to
- Remove unnecessary REG_RESERVED
- Add REG_NOSUPPORT for 32bit

Changes since V2:
- Make the setup_pebs_sample_data() a function pointer argument
- Use cpuc->pebs_record_size unconditionally
- Correct the Author of "perf/x86: Support constraint ranges"

Changes since V1:
- Avoid the interface changes for perf_reg_value() and
- Remove the extra_regs in struct perf_sample_data.
- Add struct x86_perf_regs
- Add has_xmm_regs to indicate the specific platform which support XMM
registers collection.
- Add check in x86_pmu_hw_config() to reject invalid config of regs_user
and regs_intr.
- Rename intel_hsw_weight and intel_hsw_transaction
- Add missed inline for intel_get_tsx_transaction()
- Add new patch to extract code of event update in short period
- Code rebase on top of c634dc6bdede
- Rename @d to pebs_data_cfg
- Make pebs_update_adaptive_cfg readable
- Clear pebs_data_cfg and pebs_record_size for first PEBS in add
- Don't clear ICL_EVENTSEL_ADAPTIVE. Rely on MSR_PEBS_CFG settings
- Change PEBS record parsing order (bug fix)
- Support struct x86_perf_regs
- make get_pebs_status generic
- specific intel_pmu_drain_pebs_icl()
- Use cpuc->pebs_record_size to replace format_size
- Use 'size' to replace 'range_end' for constraint ranges
- Add x86_pmu.has_xmm_regs = true;
- Add more explanation in change log of REMOVE transaction
- Make perf_regs.h consistent between kernel and user space

Andi Kleen (2):
perf/x86/intel: Extract memory code PEBS parser for reuse
perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them

Kan Liang (9):
perf/x86: Fix wrong PEBS_REGS
perf/x86: Support outputting XMM registers
perf/x86/intel/ds: Extract code of event update in short period
perf/x86/intel: Support adaptive PEBSv4
perf/x86/intel: Add Icelake support
perf/x86/intel/cstate: Add Icelake support
perf/x86/intel/rapl: Add Icelake support
perf/x86/msr: Add Icelake support
perf/x86/intel/uncore: Add Intel Icelake uncore support

Peter Zijlstra (1):
perf/x86: Support constraint ranges

arch/x86/events/core.c | 15 +
arch/x86/events/intel/core.c | 117 +++++-
arch/x86/events/intel/cstate.c | 2 +
arch/x86/events/intel/ds.c | 501 ++++++++++++++++++++++----
arch/x86/events/intel/lbr.c | 35 +-
arch/x86/events/intel/rapl.c | 2 +
arch/x86/events/intel/uncore.c | 6 +
arch/x86/events/intel/uncore.h | 1 +
arch/x86/events/intel/uncore_snb.c | 91 +++++
arch/x86/events/msr.c | 1 +
arch/x86/events/perf_event.h | 113 ++++--
arch/x86/include/asm/intel_ds.h | 2 +-
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/perf_event.h | 49 ++-
arch/x86/include/uapi/asm/perf_regs.h | 23 +-
arch/x86/kernel/perf_regs.c | 27 +-
16 files changed, 882 insertions(+), 104 deletions(-)


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