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SubjectRe: [PATCH RESEND] clk: tegra: Don't enable already enabled PLLs
Quoting Dmitry Osipenko (2019-04-19 04:42:26)
> Initially Common Clock Framework isn't aware of the clock-enable status,
> this results in enabling of clocks that were enabled by bootloader. This
> is not a big deal for a regular clock-gates, but for PLL's it may have
> some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
> clock) may result in extra long period of PLL re-locking.
> Acked-by: Peter De Schrijver <>
> Signed-off-by: Dmitry Osipenko <>
> ---

Applied to clk-next

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