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SubjectRe: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
Quoting Paul Cercueil (2019-04-17 04:24:20)
> The pixel clock is directly connected to the output of the PLL, and not
> to the /2 divider.
> Cc:
> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> Signed-off-by: Paul Cercueil <>
> ---

Is this breaking something in 5.1-rc series? Or just found by
inspection? I'm trying to understand the priority of this patch.

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