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Subject[PATCH v2 08/15] [media] mtk-mipicsi: enable/disable ana clk
Date
This patch enable/disable ana clk when power on/off

Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)

diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index c92ffe6684ef..8a4079f0ed9b 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -163,6 +163,41 @@ struct mtk_mipicsi_dev {
V4L2_MBUS_PCLK_SAMPLE_FALLING | \
V4L2_MBUS_DATA_ACTIVE_HIGH)

+static void mtk_mipicsi_ana_clk_enable(void __iomem *base, bool enable)
+{
+ if (enable) {
+ writel(1UL | readl(base + MIPI_RX_ANA00_CSI),
+ base + MIPI_RX_ANA00_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA04_CSI),
+ base + MIPI_RX_ANA04_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA08_CSI),
+ base + MIPI_RX_ANA08_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA0C_CSI),
+ base + MIPI_RX_ANA0C_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA10_CSI),
+ base + MIPI_RX_ANA10_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA20_CSI),
+ base + MIPI_RX_ANA20_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA24_CSI),
+ base + MIPI_RX_ANA24_CSI);
+ } else {
+ writel(~1UL & readl(base + MIPI_RX_ANA00_CSI),
+ base + MIPI_RX_ANA00_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA04_CSI),
+ base + MIPI_RX_ANA04_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA08_CSI),
+ base + MIPI_RX_ANA08_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA0C_CSI),
+ base + MIPI_RX_ANA0C_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA10_CSI),
+ base + MIPI_RX_ANA10_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA20_CSI),
+ base + MIPI_RX_ANA20_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA24_CSI),
+ base + MIPI_RX_ANA24_CSI);
+ }
+}
+
static int get_subdev_register(const struct soc_camera_device *icd,
struct v4l2_dbg_register *reg)
{
@@ -796,6 +831,8 @@ static int mtk_mipicsi_pm_suspend(struct device *dev)
for (i = 0; i < mipicsi->clk_num; ++i)
clk_disable_unprepare(mipicsi->clk[i]);

+ mtk_mipicsi_ana_clk_enable(mipicsi->ana, false);
+
if (mipicsi->larb_pdev != NULL)
mtk_smi_larb_put(mipicsi->larb_pdev);

@@ -833,6 +870,8 @@ static int mtk_mipicsi_pm_resume(struct device *dev)
return ret;
}

+ mtk_mipicsi_ana_clk_enable(mipicsi->ana, true);
+
/* enable digtal clock */
for (i = 0; i < mipicsi->clk_num; ++i)
(void)clk_prepare_enable(mipicsi->clk[i]);
--
2.18.0
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