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SubjectRe: [PATCH v3 05/11] PCI: dwc: imx6: Share PHY debug register definitions
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Am Sonntag, den 31.03.2019, 21:25 -0700 schrieb Andrey Smirnov:
> Both pcie-designware.c and pci-imx6.c contain custom definitions for
> PHY debug registers R0/R1 and on top of that there's already a
> definition for R0 in pcie-designware.h. Move all of the definitions to
> pcie-designware.h. No functional change intended.
>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Cc: Chris Healy <cphealy@gmail.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>
> > Cc: Leonard Crestez <leonard.crestez@nxp.com>
> > Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  drivers/pci/controller/dwc/pci-imx6.c        |  6 ++----
>  drivers/pci/controller/dwc/pcie-designware.c | 12 +++---------
>  drivers/pci/controller/dwc/pcie-designware.h |  3 +++
>  3 files changed, 8 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 92c40c250a34..bb95a3273ca2 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -103,8 +103,6 @@ struct imx6_pcie {
>  
>  /* PCIe Port Logic registers (memory-mapped) */
>  #define PL_OFFSET 0x700
> -#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
> -#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
>  
>  #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
>  #define PCIE_PHY_CTRL_DATA_LOC 0
> @@ -839,8 +837,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
>  
>  err_reset_phy:
> >   dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
> > - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
> > - dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
> > + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
> > + dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
> >   imx6_pcie_reset_phy(imx6_pcie);
> >   return ret;
>  }
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 31f6331ca46f..086e87a40316 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -14,12 +14,6 @@
>  
>  #include "pcie-designware.h"
>  
> -/* PCIe Port Logic registers */
> > -#define PLR_OFFSET 0x700
> > -#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
> > -#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
> > -#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
> -
>  int dw_pcie_read(void __iomem *addr, int size, u32 *val)
>  {
> >   if (!IS_ALIGNED((uintptr_t)addr, size)) {
> @@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci)
> >   if (pci->ops->link_up)
> >   return pci->ops->link_up(pci);
>  
> > - val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
> > - return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
> > - (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
> > + val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
> > + return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
> > + (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
>  }
>  
>  void dw_pcie_setup(struct dw_pcie *pci)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 377f4c0b52da..662bb9082c76 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -41,6 +41,9 @@
> >  #define PCIE_PORT_DEBUG0 0x728
> >  #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
> >  #define PORT_LOGIC_LTSSM_STATE_L0 0x11
> > +#define PCIE_PORT_DEBUG1 0x72C
> > +#define PCIE_PORT_DEBUG1_LINK_UP (0x1 << 4)
> > +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING (0x1 << 29)
>  
> >  #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
> >  #define PORT_LOGIC_SPEED_CHANGE BIT(17)

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