Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off | Date | Thu, 11 Apr 2019 13:24:46 -0700 |
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Quoting Weiyi Lu (2019-03-04 21:05:46) > From: James Liao <jamesjj.liao@mediatek.com> > > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. > > On MT8173 for example, ARMPLL's enable bit can be controlled by > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > set ARMPLL's enable bit as 0. In this case, SW may want and can > still change ARMPLL's rate by changing its pcw and postdiv settings. > But without this patch, new pcw setting will not be applied because > its enable bit is 0. > > Signed-off-by: James Liao <jamesjj.liao@mediatek.com> > Acked-by: Michael Turquette <mturuqette@baylibre.com> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > ---
Applied to clk-next
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