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SubjectRe: [PATCH V5 08/12] perf/x86/intel: Add Icelake support
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On 4/8/2019 11:45 AM, Liang, Kan wrote:
>
>
> On 4/8/2019 11:06 AM, Peter Zijlstra wrote:
>> On Tue, Apr 02, 2019 at 12:45:05PM -0700, kan.liang@linux.intel.com
>> wrote:
>>> +static struct event_constraint *
>>> +icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
>>> +              struct perf_event *event)
>>> +{
>>> +    /*
>>> +     * Fixed counter 0 has less skid.
>>> +     * Force instruction:ppp in Fixed counter 0
>>> +     */
>>> +    if ((event->attr.precise_ip == 3) &&
>>> +        ((event->hw.config & X86_RAW_EVENT_MASK) == 0x00c0))
>>> +        return &fixed_counter0_constraint;
>>
>> Does that want to be:
>>
>>         event->hw.config == X86_CONFIG(.event=0xc0)
>>
>> ?
>>
>> That is, are there really bits we want to mask in there?
>
> For instruction event, right, we don't need mask it.
> I will change it.
>

Actually, we have to mask some bits here, e.g.
ARCH_PERFMON_EVENTSEL_INT, ARCH_PERFMON_EVENTSEL_USR and
ARCH_PERFMON_EVENTSEL_OS. Those bits will be set in hw_config().

Also, other filds, e.g the INV, ANY, E, or CMASK fields are not allowed
for reduced Skid PEBS.


diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index dae3d84..3fa36c9 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3463,6 +3463,9 @@ hsw_get_event_constraints(struct cpu_hw_events
*cpuc, int idx,
return c;
}

+#define EVENT_CONFIG(config) \
+ (config & (X86_ALL_EVENT_FLAGS | INTEL_ARCH_EVENT_MASK))
+
static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
struct perf_event *event)
@@ -3472,7 +3475,7 @@ icl_get_event_constraints(struct cpu_hw_events
*cpuc, int idx,
* Force instruction:ppp in Fixed counter 0
*/
if ((event->attr.precise_ip == 3) &&
- (event->hw.config == X86_CONFIG(.event=0xc0)))
+ (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)))
return &fixed_counter0_constraint;

return hsw_get_event_constraints(cpuc, idx, event);
Thanks,
Kan

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