Messages in this thread | | | Subject | Re: [PATCH] misc: rtsx: Fixed rts5260 power saving parameter and sd glitch | From | Kai-Heng Feng <> | Date | Wed, 10 Apr 2019 15:47:14 +0800 |
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at 16:56, ricky_wu@realtek.com wrote:
> From: RickyWu <ricky_wu@realtek.com> > > this patch fixes rts5260 power saving parameter > make power saving function work on L1.1, L1.2 > > Signed-off-by: RickyWu <ricky_wu@realtek.com> > --- > drivers/misc/cardreader/rts5260.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/drivers/misc/cardreader/rts5260.c > b/drivers/misc/cardreader/rts5260.c > index da22bcb62b04..b510d3f46587 100644 > --- a/drivers/misc/cardreader/rts5260.c > +++ b/drivers/misc/cardreader/rts5260.c > @@ -195,7 +195,7 @@ static int sd_set_sample_push_timing_sd30(struct > rtsx_pcr *pcr) > | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); > rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); > rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, > - CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); > + CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
Just a nit, seems to be an unnecessary change.
> rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); > > return 0; > @@ -238,8 +238,8 @@ static int rts5260_card_power_on(struct rtsx_pcr > *pcr, int card) > /* Reset SD_CFG3 register */ > rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); > rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, > - SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 | > - SD30_CLK_STOP_CFG0, 0); > + SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 | > + SD30_CLK_STOP_CFG0, 0);
Ditto.
> > rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0); > > @@ -315,12 +315,12 @@ static void rts5260_init_ocp(struct rtsx_pcr *pcr) > > > rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL, > - RTS5260_DVCC_OCP_THD_MASK, > - option->sd_800mA_ocp_thd); > + RTS5260_DVCC_OCP_THD_MASK, > + option->sd_800mA_ocp_thd);
Ditto.
> > rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG, > - RTS5260_DV331812_OCP_THD_MASK, > - RTS5260_DV331812_OCP_THD_270); > + RTS5260_DV331812_OCP_THD_MASK, > + RTS5260_DV331812_OCP_THD_270);
Ditto.
That said, the patch works, Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
> > mask = SD_OCP_GLITCH_MASK; > val = pcr->hw_param.ocp_glitch; > @@ -451,6 +451,7 @@ static void rts5260_pwr_saving_setting(struct > rtsx_pcr *pcr) > lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN) > | rtsx_check_dev_flag(pcr, PM_L1_2_EN); > > + rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); > if (lss_l1_2) { > pcr_dbg(pcr, "Set parameters for L1.2."); > rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL, > @@ -573,10 +574,10 @@ static int rts5260_extra_init_hw(struct rtsx_pcr > *pcr) > * to drive low, and we forcibly request clock. > */ > if (option->force_clkreq_0) > - rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, > + rtsx_pci_write_register(pcr, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); > else > - rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, > + rtsx_pci_write_register(pcr, PETXCFG, > FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); > > return 0; > @@ -704,7 +705,7 @@ void rts5260_init_params(struct rtsx_pcr *pcr) > option->ocp_en = 1; > if (option->ocp_en) > hw_param->interrupt_en |= SD_OC_INT_EN; > - hw_param->ocp_glitch = SDVIO_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U; > + hw_param->ocp_glitch = SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U; > option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550; > option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970; > } > -- > 2.17.1
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