Messages in this thread | | | Date | Mon, 1 Apr 2019 09:30:24 +0200 | From | Peter Zijlstra <> | Subject | Re: [patch 04/14] x86/exceptions: Make IST index zero based |
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On Sun, Mar 31, 2019 at 11:40:24PM +0200, Thomas Gleixner wrote: > --- a/arch/x86/include/asm/page_64_types.h > +++ b/arch/x86/include/asm/page_64_types.h > @@ -25,11 +25,14 @@ > #define IRQ_STACK_ORDER (2 + KASAN_STACK_ORDER) > #define IRQ_STACK_SIZE (PAGE_SIZE << IRQ_STACK_ORDER) > > -#define DOUBLEFAULT_STACK 1 > -#define NMI_STACK 2 > -#define DEBUG_STACK 3 > -#define MCE_STACK 4 > -#define N_EXCEPTION_STACKS 4 /* hw limit: 7 */ > +/* > + * The index for the tss.ist[] array. The hardware limit is 7 entries. > + */ > +#define DOUBLEFAULT_IST 0 > +#define NMI_IST 1 > +#define DEBUG_IST 2 > +#define MCE_IST 3 > +#define N_EXCEPTION_STACKS 4
Would it make sense to use an enum here?
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