lkml.org 
[lkml]   [2019]   [Mar]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH AUTOSEL 4.4 17/21] x86/cpu/cyrix: Use correct macros for Cyrix calls on Geode processors
    Date
    From: Matthew Whitehead <tedheadster@gmail.com>

    [ Upstream commit 18fb053f9b827bd98cfc64f2a35df8ab19745a1d ]

    There are comments in processor-cyrix.h advising you to _not_ make calls
    using the deprecated macros in this style:

    setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);

    This is because it expands the macro into a non-functioning calling
    sequence. The calling order must be:

    outb(CX86_CCR2, 0x22);
    inb(0x23);

    From the comments:

    * When using the old macros a line like
    * setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
    * gets expanded to:
    * do {
    * outb((CX86_CCR2), 0x22);
    * outb((({
    * outb((CX86_CCR2), 0x22);
    * inb(0x23);
    * }) | 0x88), 0x23);
    * } while (0);

    The new macros fix this problem, so use them instead. Tested on an
    actual Geode processor.

    Signed-off-by: Matthew Whitehead <tedheadster@gmail.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Cc: luto@kernel.org
    Link: https://lkml.kernel.org/r/1552596361-8967-2-git-send-email-tedheadster@gmail.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/x86/kernel/cpu/cyrix.c | 14 +++++++-------
    1 file changed, 7 insertions(+), 7 deletions(-)

    diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
    index 15e47c1cd412..6e4e4191abb5 100644
    --- a/arch/x86/kernel/cpu/cyrix.c
    +++ b/arch/x86/kernel/cpu/cyrix.c
    @@ -121,7 +121,7 @@ static void set_cx86_reorder(void)
    setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */

    /* Load/Store Serialize to mem access disable (=reorder it) */
    - setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
    + setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
    /* set load/store serialize from 1GB to 4GB */
    ccr3 |= 0xe0;
    setCx86(CX86_CCR3, ccr3);
    @@ -132,11 +132,11 @@ static void set_cx86_memwb(void)
    printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");

    /* CCR2 bit 2: unlock NW bit */
    - setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
    + setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
    /* set 'Not Write-through' */
    write_cr0(read_cr0() | X86_CR0_NW);
    /* CCR2 bit 2: lock NW bit and set WT1 */
    - setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);
    + setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
    }

    /*
    @@ -150,14 +150,14 @@ static void geode_configure(void)
    local_irq_save(flags);

    /* Suspend on halt power saving and enable #SUSP pin */
    - setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);
    + setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);

    ccr3 = getCx86(CX86_CCR3);
    setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */


    /* FPU fast, DTE cache, Mem bypass */
    - setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);
    + setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
    setCx86(CX86_CCR3, ccr3); /* disable MAPEN */

    set_cx86_memwb();
    @@ -292,7 +292,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
    /* GXm supports extended cpuid levels 'ala' AMD */
    if (c->cpuid_level == 2) {
    /* Enable cxMMX extensions (GX1 Datasheet 54) */
    - setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);
    + setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);

    /*
    * GXm : 0x30 ... 0x5f GXm datasheet 51
    @@ -315,7 +315,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
    if (dir1 > 7) {
    dir0_msn++; /* M II */
    /* Enable MMX extensions (App note 108) */
    - setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
    + setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
    } else {
    /* A 6x86MX - it has the bug. */
    set_cpu_bug(c, X86_BUG_COMA);
    --
    2.19.1
    \
     
     \ /
      Last update: 2019-03-30 01:59    [W:4.119 / U:0.084 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site