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SubjectRe: [PATCH 09/14] bus: ti-sysc: Move rstctrl reset to happen later
Hi Tony,

On 3/26/19 6:40 PM, Tony Lindgren wrote:
> Hi,
> * Suman Anna <> [190326 23:22]:
>> On 3/26/19 6:13 PM, Tony Lindgren wrote:
>> Hmm, are you envisioning the SYSC reset (OCP SoftReset) here or the PRCM
>> RSTCTRL hardresets here? The latter in general requires the clocks to be
>> running first (module won't be in ready status until you deassert the
>> hardresets with clocks running). You can look up the Warm-reset or
>> Cold-reset sequences in the TRMs for any of the processors.
> That's for rstctrl. I just did a quick test with my earlier
> reset-simple patch and I noticed sgx on am33xx produces a
> clock error unless we deassert it's rstrctrl before enabling
> clocks first:
> gfx-l3-clkctrl:0004:0: failed to enable

Yeah, and I see a similar one across the other modules controlled by
RSTCTRL bits for me as well - MMUs, PRUSS etc. This is because you can
only check the module ready status in _omap4_clkctrl_clk_enable() only
both after the clocks are turned on and resets are deasserted. That
check will always fail with rstctrl asserted. The omap_hwmod code does
use the reset status checks for bailing out, but that stuff is not
present in clkctrl code and can only be achieved by adding a
CLKF_NO_IDLEST (somewhat misnamed) to the corresponding clkctrl atm.

See [1] for AM33xx SGX. I will be posting some of these once I check the

>> I am working on preparing the next version of PRUSS patches with ti-sysc
>> on AM33xx/AM437x/AM57xx platforms, so will pick up these patches for my
>> testing.
> OK great, yes please check and test with your rstctrl use case.
> I guess you still need to use the reset-simple patch for now
> until we have a proper prm rstctrl driver.
> Note that you probably also want to leave out the struct
> omap_hwmod data from omap_hwmod_*_data.c files with rstctrl
> entries.

You mean no hwmod entries at all, or hwmod entries with no rstctrl data?



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